Command, address and write data signals are typically coupled from a memory controller or other device to memory devices, such as synchronous random access memory (“SDRAM”) devices. These command, address and write data signals are typically transmitted in synchronism with a system clock signal. Similarly, read data signals are typically coupled from memory devices to a memory controller or other device in synchronism with the system clock signal. In some cases, the memory devices or memory controller may couple a strobe signal between the memory devices and memory controller along with the command, address and data signals. The system clock signal or strobe signal derived from the system clock signal is used to “capture” the command, address and data signals by clocking latches that store the command, address and data signals. The advantage of coupling a strobe signal between the memory devices and memory controller is that it will be affected by signal skews and propagation delays in the same manner that with the command, address and data signals with which it is transmitted will be affected.
The transitions of the system clock signal are typically substantially aligned with transitions of the command, address and data signals. Similarly, the transitions of a received strobe signal are typically substantially aligned with transitions of the command, address and data signals. During the period between these transitions, the command, address and data signals are “valid,” and it is during this valid period, known as an “eye,” that the command, address and data signals must be captured. The system clock signal or received strobe signal normally cannot be used to directly capture command, address and data signals because the transitions of the system clock signal or received strobe signal substantially coincide with the transitions of the command, address and data signals rather than the eye between those transitions. As a result, a quadrature strobe signal that is delayed from the system clock or received strobe signal by 90 degrees must be generated from the system clock signal or received strobe signal. The quadrature strobe signal can latch the command, address and write data signals into the memory device at the center of the “eye” in which the command, address or data signals are valid.
Various techniques have been used to generate a quadrature strobe signal in a memory device or memory controller based on a system clock signal. If the frequency of the system clock signal is fixed, a quadrature strobe signal can be generated by a timing circuit that simply generates a transition of the strobe signal a fixed time after a corresponding transition of the system clock signal. However, synchronous memory devices are typically designed and sold to be operated over a wide range of system clock frequencies. Therefore, it is generally not practical to use a fixed timing circuit to generate a quadrature strobe signal from the system clock signal. Instead, as a practical matter, a circuit that can adapt itself to a system clock signal having a range of frequencies must be used.
One technique that has been used to ensure the correct timing of a strobe signal relative to captured digital signals is to use a closed loop circuit, such as a phase-lock loop (“PLL”) or delay-lock loop (“DLL”), to generate the quadrature strobe signal. In particular, a closed loop circuit allows the timing of the strobe signal to be adjusted to minimize the phase error between the quadrature strobe signal and the valid eye of the digital signal. Although these closed loop circuits can accurately generate a quadrature strobe signal based on the system clock signal over a substantial range of frequencies of the system clock signal, they are not without their limitations. For example, the propagation delays of the command, address and data signals coupled between a memory controller and a memory device may vary to such an extent that a quadrature strobe signal generated from the system clock can no longer capture these signals during their valid period or eye. A quadrature strobe signal that is generated from a strobe signal coupled from the memory controller or memory device with the transmitted the command, address or data signals can better track variations in the propagation times of the command, address or data signals. However, the phase of the quadrature strobe signal generated from the strobe signal coupled with the transmitted command, address or data signals may not adequately track variations in the propagation times of the transmitted command, address or data signals. The quadrature strobe signal may be further delayed relative to the command, address or data signals in coupling the quadrature strobe from the closed loop circuit generating the strobe signal to a latch that will be used to capture the transmitted command, address or data signals. Therefore, even a quadrature strobe signal generated from a strobe signal transmitted with the command, address or data signals may fail to capture these signals during their valid period or eye. As the speed of memory devices continues to increase, the “eye” during which the command, address and data signals must be captured becomes smaller and smaller, thus making the timing of the quadrature strobe signal even more critical. Capturing command, address and data signals during the eye becomes even more difficult in memory devices and memory controllers in which several bits of data are serially coupled from an external terminal each clock period.
There is therefore a need for a system and method for more precisely capturing transmitted command, address and data signals during their eye or valid period, particularly where multiple bits of a command, address or data are transmitted during each clock period.